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In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3. S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET DEC — Decrement DEC dst Operation: dst . dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, dst value is – 128 (80H) and result value is + 127 (7FH); cleared otherwise. Format: Bytes Cycles Opcode Addr Mode (Hex) dst opc dst 2 4 00 R 4 01 IR Examples: Given: R1 = 03H and register 03H = 10H: DEC R1 . R1 = 02H DEC @R1 . Register 03H = 0FH In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH. SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 DI — Disable Interrupts DI Operation: SYM (2) . 0 Bit zero of the system mode register, SYM.2 更多：https://www.bmcx.com/ , is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 8F Example: Given: SYM = 04H: DI If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register and clears SYM.2 to "0", disabling interrupt processing. S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET EI — Enable Interrupts EI Operation: SYM (2) . 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 9F Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 04H, enabling all interrupts. (SYM.2 is the enable bit for global interrupt processing.) SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst src opc 1 4 6F – – Example: The instruction IDLE NOP NOP NOP stops the CPU clock but not the system clock. S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET INC — Increment INC dst Operation: dst . dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is dst value is + 127 (7FH) and result is – 128 (80H); cleared otherwise.