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LDC (note) 1105H,R0 ; 11H (contents of R0) is loaded into program memory location; 1105H, (1105H) . 11H LDE 1105H,R0 ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) . 11H NOTE: These instructions are not supported by masked ROM type devices. S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst . src rr . rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst src opc dst | src 2 10 E2 r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 . RR6 – 1) LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 . RR6 – 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 LDCI/LDEI — LOAD MEMORY AND INCREMENT LDCI/LDEI dst,src Operation: dst . src rr . rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes "Irr" even for program memory and odd for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst src opc dst | src 2 10 E3 r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 . RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 . RR6 + 1) ; R8 = 0DDH 更多：https://www.bmcx.com/ , R6 = 10H, R7 = 34H S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time. SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 OR — Logical OR OR dst,src Operation: dst . dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". Format: Bytes Cycles Opcode Addr Mode (Hex) dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44RR 6 45 RIR opc dst src 3 6 46 RIM Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR R0,R1 . R0 = 3FH, R1 = 2AH OR R0,@R2 . R0 = 37H, R2 = 01H, register 01H = 37H OR 00H,01H . Register 00H = 3FH, register 01H = 37H OR 01H,@00H . Register 00H = 08H, register 01H = 0BFH OR 00H,#02H . Register 00H = 0AH In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.