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Format: Bytes Cycles Opcode Addr Mode (Hex) dst dst | opc 1 4 rE r r = 0 to F opc dst 2420 R 4 21 IR Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC R0 . R0 = 1CH INC 00H . Register 00H = 0DH INC @R0 . R0 = 1BH, register 01H = 10H In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 IRET — Interrupt Return IRET IRET Operation: FLAGS . @SP SP . SP + 1 PC . @SP SP . SP + 2 SYM(2) . 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred). Format: IRET Bytes Cycles Opcode (Normal) (Hex) opc 1 10 BF 12 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC . dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: No flags are affected. Format: (1) Bytes Cycles Opcode Addr Mode (2) (Hex) dst cc | opc dst 3 8 ccD DA cc = 0 to F opc dst 2 8 30 IRR NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the op code are both four bits. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP C,LABEL_W . LABEL_W = 1000H, PC = 1000H JP @00H . PC = 0120H The first example shows a conditional JP. Assuming that the carry flag is set to "1" 更多：https://www.bmcx.com/ , the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H. SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 JR — Jump Relative JR cc,dst Operation: If cc is true, PC . PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes). The range of the relative address is + 127, – 128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (note) (Hex) dst cc | opc dst 2 6 ccB RA cc = 0 to F NOTE: In the first byte of the two-byte instruction format, the condition code and the op code are each four bits. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X . PC = 1FF7H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.