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SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDC dst,src Load program memory LDE dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement LDCI dst,src Load program memory and increment LDEI dst,src Load external data memory and increment POP dst Pop from stack PUSH src Push to stack Arithmetic Instructions ADC dst,src Add with carry ADD dst,src Add CP dst,src Compare DEC dst Decrement INC dst Increment SBC dst,src Subtract with carry SUB dst,src Subtract Logic Instructions AND dst,src Logical AND COM dst Complement OR dst,src Logical OR XOR dst,src Logical exclusive OR S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL dst Call procedure IRET Interrupt return JP cc,dst Jump on condition code JP dst Jump unconditional JR cc 更多：https://www.bmcx.com/ ,dst Jump relative on condition code RET Return Bit Manipulation Instructions TCM dst,src Test complement under mask TM dst,src Test under mask Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SCF Set carry flag STOP Enter stop mode SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result. System Flags Register (FLAGS) D5H, R/W .7 .6 .5 .4 .3 .2 .1 .0MSB LSB Carry flag (C) Zero flag (Z) Sign flag (S) Overflow flag (V) Not mapped